Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) today announced that they will standardize on a verification methodology based on the IEEE Std. 1800™-2005 SystemVerilog standard. The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code format.
Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries. The methodology will be made available under a standard open-source license, Apache™ License, Version 2.0.
15:32:59 星期二
