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楼主 问题： FPGA 与 CPLD的比较？ 发布时间： 2002-11-6 下午4:06

作者： tibetlee

等级： 初入江湖

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能否较为详细和清晰的介绍一下FPGA与CPLD的不同之处和相同之处，比如时延、内部结构以及设计方法？
引用 回复 鲜花 ( 0) 臭鸡蛋 ( 0)
发布时间： 2002-11-7 下午2:52

专家： 莫柱昌先生

职务： Xilinx亚太区产品营销经理

The major difference between FPGA and CPLD is the routing mechanism.

The routing delay is fixed within CPLD, so that all CPLD vendors emphasize on what is the time delay from I/O to I/O pin. So that the logic placement within the CPLD
is not a factor to affect the result of the running clock frequency. The running clock frequency within CPLD depends on "how many logic level needs to go through".

On the other hand, the routing delay within FPGA is not a fixed value. So the placement of the logic within the FPGA will affect the result of the clock performance. Therefore, the running clock frequency within FPGA depends on three factors
(a) placement
(b) routing path delay/Logic Cell delay (i.e. 4-input look up table and register)
(3) logic complexity.
"Logic complexity" is more or less customer dependents (in order
to help customer, PLD vendor provides IP core in order to mimimum the logic level). "Placement" is a mix of how good is the PLD vendor's propierty software and designer manual control the placement. For "Routing path Delay/logic cell delay"
that is what PLD vendor invests most time and money on, such as Copper layer, reduce the K factor(dielectric factor), advance technology (0.13um).

On the product itself, FPGA is based on Look-Up table to provide result, on the other hand CPLD is based on "SUM OF PRODUCT TERMS" architecture ("AND"/"OR"). FPGA is SRAM base, meanwhile CPLD is either FLASH or EEPROM base.

For the similarity, I personnally do not see common point on this two devices except both is programmable.

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