|
|
 |
|
我写了一个verilog程序,当使用4个IF ELSE的时候烧到CPLD里可以用,当是写了5个或者5个以上就不能用...使用CASE语句也是如此...但是仿真是正常的...我用的CPLD是LC4128V144pin
这个程序主要是用一个时钟产生一系列波形的程序.
下面是代码:
module test(clk,LE1,LE2,LE3,LE4,LE5,LE6,LE7,LE8);
input clk;
output LE1,LE2,LE3,LE4,LE5,LE6,LE7,LE8;
reg LE1,LE2,LE3,LE4,LE5,LE6,LE7,LE8;
reg[7:0] state;
parameter S1 = 8'b00000001,
S2 = 8'b00000010,
S3 = 8'b00000100,
S4 = 8'b00001000,
S5 = 8'b00010000,
S6 = 8'b00100000,
S7 = 8'b01000000,
S8 = 8'b10000000,
high = 1,
low = 0;
always @(negedge clk)
begin
if(state==S1)
begin
LE1<=low;
LE2<=high;
LE3<=high;
LE4<=high;
LE5<=high;
LE6<=high;
LE7<=high;
LE8<=high;
state<=S2;
end
else if(state==S2)
begin
LE1<=~LE1;
LE2<=~LE2;
state<=S3;
end
else if(state==S3)
begin
LE2<=~LE2;
LE3<=~LE3;
state<=S4;
end
else if(state==S4)
begin
LE3<=~LE3;
LE4<=~LE4;
state<=S5; //state<=S1;
end
else if(state==S5) //当把这段
begin //语句
LE4<=~LE4; // 去掉
LE5<=~LE5; //并把
state<=S1; //上面的 state<=S5
end //改成state<=S1就可以用了
else state<=S1;
end
endmodule
|
|
